1. Field of the Invention
This invention relates to the field of flip-flops, and particularly to master-slave flip-flops and methods to improve their timing margins.
2. Description of the Related Art
A master-slave flip-flop 10, such as that shown in FIG. 1, is formed by connecting a first D latch 12—the “master”—in series with a second D latch 14—the “slave”, and clocking the latches with complementary clocks CKM and CKS, respectively. For a negative-edge triggered master-slave flip-flop, a signal applied to each latch's D input is transferred to its Q output—i.e., the latch is “transparent”—when its clock is high, and the latch “locks” an applied input signal when its clock is low. Thus, a signal applied to the D input of master latch 12 is transferred to slave latch 14 when CKM is high, is latched by master latch 12 and transferred to the Q output of slave latch 14 when CKM goes low and CKS goes high, and is latched by slave latch 14 when CKS goes low. Since CKM and CKS are complementary, the master-slave flip-flop is never fully transparent.
Master-slave flip-flops are widely used. One application in which they are commonly found is that of a memory register, which employs multiple master-slave flip-flops to store respective data bits. Some memory registers, such as those found in DDR2/3 DRAM devices, must comply with specifications promulgated by the JEDEC Solid State Technology Association. One parameter so specified is that of propagation delay (tpd), which is defined as the delay between the toggling of an input clock (CKin) from which CKM and CKS are derived, and a resulting change at the slave latch's output. For some high-speed memory systems, the tpd specification may be necessarily short, and difficult or impossible for some master-slave flip-flops to meet.